CMOS circuits are used in a variety of integrated circuit (IC) applications. A CMOS process can be used to fabricate many different sorts of functionality, such as memory, logic, and switching, and thus CMOS techniques are particularly desirable in applications where an IC includes several different types of functional blocks.
One family of ICs employing CMOS fabrication techniques are programmable logic devices (PLDs). PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
CMOS technology has been shrinking, that is, the devices and the separation between devices has been getting smaller. The type of spacing used to produce a CMOS IC is commonly called a “technology”, such as 180-nano-meter (“nm”) technology, and generally represents the minimum spacing between nodes on the physical device. IC technologies of 90 nm and less are generally referred to as “deep submicron” technologies.
SRAM is often used in ICs because it offers speed advantages over DRAM arrays. SRAM cells generally can use the smallest transistor size in each technology generation. SRAM is a more expensive alternative than DRAM, but is desirable where speed is a principal consideration. SRAM is also easier to interface to and allows less constrained (i.e., truly random) access, compared to modern types of DRAM.
An exemplary SRAM cell has two half cells, each half cell having an NMOS device with a gate connected to the gate of a PMOS cell. An access device (e.g., another NMOS device) in the half cell is gated by the word line (“WL”) and couples the data state of the half cell to a bit line (“N Bit or N bar Bit”) of the memory array. As SRAM cell design shrinks into the submicron and deep submicron range, variations in cell performance arise from minor differences in the fabrication processes. One effect of typical process variation is that the NMOS devices in a cell might operate faster or slower than the PMOS devices, or the transistors in the two half cells do not match with each other. The operating speed ratio can vary across an SRAM array due to runout and similar effects. A “fast” device has a lower threshold voltage (“VTH”) and generally transfers more charge (or produces more current) during a READ or WRITE operation than a slower device.
SRAM cell design is constrained by a worst-case corner for a READ disturbance when the NMOS devices are fast, and the PMOS devices are slow, called a Fast-Slow (“FS”) corner, and a worst-case corner for a WRITE difficulty when the NMOS devices are slow, and the PMOS devices are fast, called a SF corner.
One approach to satisfying both FS and SF operation of SRAM cells in a memory array is to increase the physical size of the memory cells. However, this is contrary to the desired advantages (e.g., higher cell density per silicon area) by using the smaller node technology. Data on 45-nm technology indicates that SRAM cell size might have to increase as much as 20% from the scaled cell size according to the design route checker (“DRC”) limitation.
FIG. 1 is a circuit diagram of a portion of an SRAM memory 100 illustrating another approach that has been proposed to improve SRAM operation. The SRAM memory 100 includes statically ON NMOS devices 102, 104, 106, 108 that couple wordlines 110, 112 of the SRAM memory array to ground during a READ operation. The NMOS devices 102, 104, 106, 108 are referred to as “replica access transistors” in a read assist circuit 114. The NMOS devices in the read assist circuit 114 lower the word line level when that word line is activated by the word line driver 116 during a READ operation. The NMOS devices in the read assist circuit 114 basically operate in parallel with the NMOS devices in memory cell 124 to bring the word line 112 to ground, which in turn weakly turns on the NMOS pass gate transistors 120, 122 in the memory cell 124, thus improving the SNM by increasing the effective resistance of pass gates 120 and 122 to the bit lines 126, 128. The word line voltage is lowered for improved SNM using the always ON replica transistors to provide tracking capability. Unfortunately, this approach degrades overall cell performance, as measured by the lowered READ current through the passgate, and increased static current on the active word line.
Therefore, SRAMs with improved SNM operation that avoid the disadvantages of the prior art are desirable.